Description
The sampling rates for Digital Signal Processing (DSP) in such applications as speech, telephony, mobile radio, video, radar and sonar, ranges from 10 kHz to 100 MHz. Real-time implementation of such systems requires design of hardware that can process signal samples as these are received from the source, rather than storing them in buffers for batch-mode processing. Efficient implementation of DSP hardware demands a study of families of architectures and styles, selecting an appropriate architecture for a specific application. Digit-serial computation is proposed as an appropriate design methodology when bit-serial systems cannot meet sampling rate requirements, and where bit-parallel systems require excessive hardware. A family of implementations can be obtained by changing the digit size parameter, allowing an optimum trade-off between throughput and size. This text describes the architecture and the design and layout methods used in Parsifal – the silicon compiler developed at GEC’s corporate research and development laboratory.Table of Contents: 1 Digit-Serial Architecture.- 2 Digit-Serial Cell Design.- 3 Multipliers.- 4 Digit-Serial Input Language.- 5 Layout of Digit-Serial circuits.- 6 Scheduling.- 7 Digit-Serial Performance.- 8 Bit-Level Unfolding.- 9 The Folding Transformation.- 10 Wavelet Transform Architectures.- 11 Digit-Serial Systolic Arrays.- 12 Canonic Signed Digit Arithmetic.- 13 Online Arithmetic.
